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New ContributorLow Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Exemple on the board Stratix 10 SX SoC dev
Hello, We are trying to use the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Exemple on the board Stratix 10 SX SoC devkit (H-Tile version). When we connect the board with QSFP28 cable...
Hello,
Finally, we find the solution and we share it, if it can help someone.
The problem was the FEC option. It was enable on the Alveo U250 and also on the Intel E810.
As soons as we aligne that on each side it works (Disable FEC on both side OR Enable FEC on both side).
Regards
Anthony
