ContributorHi
What is the constraint to locate all the FF in the OBUF ?
I need a minimum and constant routing latency for each synthesis
Seems like you're using Pro version. Then probably can use GPIO IP under section I/O in IP Catalog. The register mode choose DDIO.
Super ContributorFast Output Register assignment in the Assignment Editor.
Super ContributorHi,
May I know do you have any further concern or consideration?
Thanks,
Regards,
Sheng
ContributorThank you for the reply
I have 1 more question (relevant to the previous question),
I need to create a source synchronous connection between two FPGAs.
FPGA A needs to transmit 32 data bits along with a clock signal to FPGA B. All 32 bits are sampled by a PLL clock ( FPGA A )
and then sent to 32 IO_OBUF pins.
The same PLL clock, which samples the 32 data bits, is also connected to another IO_OBUF.
I would like to align the latency between the clock and the 32 data bits.
Is there an IP core or alternative method to create an ODDR that is sampled by the PLL clock and generates a new clock that is aligned with the flip-flop for the 32 data bits?
Super ContributorHi,
Probably can use DDIO IP for ODDR.
Thanks,
Regards,
Sheng
ContributorDDIO ?
There is no IP name like it in the IP catalog
Super ContributorSeems like you're using Pro version. Then probably can use GPIO IP under section I/O in IP Catalog. The register mode choose DDIO.
