JESD204B Lane Limitation

Regarding the JESD204B IP, there is an 8-lane limit which appears to relates to the MAC specifically. When using the example design, this is further reduced to 4-lanes if simulation is required as a single core is configured in Duplex mode.

- What is the reason for this limitation?

- Are there any workarounds to overcome the example design limitation (ie. is it possible to instantiate two separate cores, Tx and Rx with an 8-lane interface between them)?