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Honored Contributor
Honored ContributorIssues with Stratix IV E FPGA Dev Kit
We have a Stratix IV E FPGA Development Kit and recently started to use it. But we have several issues on the example designs included in the kit. First, its example designs are segregated i...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- As far as I know, there is no quick way to convert a VHDL or Verilog file into .bdf. --- Quote End --- I think, there's no meaningful way to convert a behavioral HDL description into a schematic, at least without considerably reducing it's readability.
