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Altera_Forum
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16 years ago

Issues with Stratix IV E FPGA Dev Kit

We have a Stratix IV E FPGA Development Kit and recently started to use it. But we have several issues on the example designs included in the kit. First, its example designs are segregated i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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As far as I know, there is no quick way to convert a VHDL or Verilog file into .bdf.

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I think, there's no meaningful way to convert a behavioral HDL description into a schematic, at least without considerably reducing it's readability.