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MinhTris's avatar
MinhTris
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Issues Converting VHDL to Verilog for DE10 Standard Board

Hi everyone,

I’m reaching out in desperation because I’m stuck on a project and really need help.

I’m working on a project inspired by a YouTube video and a GitHub project that use VHDL to implement functionality on the DE10 Standard Board. The goal is to play a 30-second audio, and the VHDL implementation works flawlessly—I’ve verified it step by step and reproduced the results shown in the video.

However, I decided to rewrite the code in Verilog for compatibility with other parts of my project. Despite spending a lot of time carefully converting the VHDL into three Verilog files (attached below) and double-checking everything, the functionality does not work as expected in Verilog.

The problem: The Verilog code fails to replicate the audio playback functionality achieved with the VHDL implementation.

I’ve spent countless hours debugging and troubleshooting but have reached a point where I feel completely lost and hopeless.

My Request:

  1. If anyone experienced in VHDL-to-Verilog conversion or DE10 Standard Board projects could take a look at my Verilog code, I would be forever grateful.
  2. Are there specific nuances or issues with using Verilog on the DE10 Standard Board compared to VHDL?
  3. Any debugging tips, insights, or suggestions would mean so much to me.

I’ve attached the Verilog files for your reference and am happy to provide additional information if needed.
Edited: I have attached 3 text files that include the VHDL code corresponding to the 3 Verilog files

Thank you so much for your time and help—I truly appreciate any support you can provide!

Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Hi,
    the VHLD is almost correctly translated, except for one assignment which apparently misplaced

    VHDL

    -- Copy the input clock signal
    aud_bk <= aud_clock_12;

    -- Main process for generating control signals and sending audio data
    process(aud_clock_12)

    Verilog

    always @(negedge(aud_clock_12)) begin
    aud_bk <= aud_clock_12;

    Asignment must be placed outside clock sensitive block, otherwise it won't generate a clock at all

    assign aud_bk = aud_clock_12;
    There's also something wrong with the Verilog PLL instantiation which seems to be mixed with onchip memory.

    pll u0 (
    .clk_clk(CLOCK_50),
    .reset_reset_n(1'b1),
    .clock_12_clk(clock_12pll),
    .onchip_memory2_0_s1_address(ROM_ADDR),
    .onchip_memory2_0_s1_clken(1'b1),
    .onchip_memory2_0_s1_chipselect(1'b1),
    .onchip_memory2_0_s1_debugaccess(1'b0),
    .onchip_memory2_0_s1_write(1'b0),
    .onchip_memory2_0_s1_readdata(ROM_OUT),
    .onchip_memory2_0_s1_writedata(16'b0),
    .onchip_memory2_0_s1_byteenable(2'b11),
    .onchip_memory2_0_reset1_reset(1'b0)
    );

    Regards
    Frank

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    the VHLD is almost correctly translated, except for one assignment which apparently misplaced

    VHDL

    -- Copy the input clock signal
    aud_bk <= aud_clock_12;

    -- Main process for generating control signals and sending audio data
    process(aud_clock_12)

    Verilog

    always @(negedge(aud_clock_12)) begin
    aud_bk <= aud_clock_12;

    Asignment must be placed outside clock sensitive block, otherwise it won't generate a clock at all

    assign aud_bk = aud_clock_12;
    There's also something wrong with the Verilog PLL instantiation which seems to be mixed with onchip memory.

    pll u0 (
    .clk_clk(CLOCK_50),
    .reset_reset_n(1'b1),
    .clock_12_clk(clock_12pll),
    .onchip_memory2_0_s1_address(ROM_ADDR),
    .onchip_memory2_0_s1_clken(1'b1),
    .onchip_memory2_0_s1_chipselect(1'b1),
    .onchip_memory2_0_s1_debugaccess(1'b0),
    .onchip_memory2_0_s1_write(1'b0),
    .onchip_memory2_0_s1_readdata(ROM_OUT),
    .onchip_memory2_0_s1_writedata(16'b0),
    .onchip_memory2_0_s1_byteenable(2'b11),
    .onchip_memory2_0_reset1_reset(1'b0)
    );

    Regards
    Frank

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    you can mix Verilog and VHLD code and check which of the three sources fail.

    I'd need the original VHDL to check where the logic has been possibly changed. I see a dubious detail in i2c.v, it's driving SDA to '1' in serveral places which should never happen. Is it also done in the VHDL code? I presume push-pull drive of SCL is copied from VHDL. It's not strictly following I2C specification but can be done in a single master system if no slave is supporting clock stretching.

    Regards
    Frank

    • MinhTris's avatar
      MinhTris
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Frank,

      Thank you so much for your reply. For your reference, I am attaching three text files that include the VHDL code corresponding to the three Verilog files (as the .vhdl extension is not supported).

      Regarding the SDA being driven to '1' in the Verilog code, my main purpose here is to translate the VHDL code to Verilog (which I need the file in the "*.v" not ".vhdl" format. In the original VHDL code, the author drives SDA to '1' in some scenarios. For example:

      -- Transmit data on SDA when SCL is LOW
if (clk_en = '1') then
    case i2c_fsm is
        when st0 => -- Idle state
            i2c_sda <= '1'; -- Keep SDA high
            i2c_busy <= '0';
            i2c_done <= '0';
            if (i2c_send_flag = '1') then
                i2c_fsm <= st1; -- Start communication
                i2c_busy <= '1';
            end if;

        when st1 => -- Send START condition
            i2c_sda <= '0';
            i2c_fsm <= st2;
            data_index <= 7;

      I translated this behavior directly into Verilog, which is why SDA is driven to '1' in the corresponding cases. If there’s a better approach or improvement you would suggest, I’m open to refining the code further to align with best practices or specific requirements.

      Thank you again for your time and guidance.