module aud_gen (
    input aud_clock_12,
    output reg aud_bk,
    output reg aud_dalr,
    output reg aud_dadat,
    input [31:0] aud_data_in
);

reg sample_flag = 0;
reg [4:0] data_index = 31; // 5-bit register to store index 0 to 31
reg [15:0] da_data = 16'b0;
reg [31:0] da_data_out = 32'b0;
reg [8:0] aud_prscl = 0; // 9-bit register for the sample rate counter
reg clk_en = 0;

always @(negedge(aud_clock_12)) begin

		
	 aud_bk <= aud_clock_12;
    // Control the aud_dalr signal
    aud_dalr <= clk_en;
	 
    // Process the sample rate logic
    if (aud_prscl < 250) begin
        aud_prscl <= aud_prscl + 1;
        clk_en <= 0;
    end else begin
        aud_prscl <= 0;
        da_data_out <= aud_data_in; // Get new sample from input data
        clk_en <= 1;
    end

    // When the clock enable is active, start sending the new sample
    if (clk_en) begin
        sample_flag <= 1;
        data_index <= 31;
    end

    // Send data bits to aud_dadat
    if (sample_flag) begin
        if (data_index > 0) begin
            aud_dadat <= da_data_out[data_index];
            data_index <= data_index - 1;
        end else begin
            aud_dadat <= da_data_out[data_index];
            sample_flag <= 0;
        end
    end

end

endmodule