Forum Discussion

MinhTris's avatar
MinhTris
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Issues Converting VHDL to Verilog for DE10 Standard Board

Hi everyone, I’m reaching out in desperation because I’m stuck on a project and really need help. I’m working on a project inspired by a YouTube video and a GitHub project that use VHDL to implemen...
Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Hi,
    the VHLD is almost correctly translated, except for one assignment which apparently misplaced

    VHDL

    -- Copy the input clock signal
    aud_bk <= aud_clock_12;

    -- Main process for generating control signals and sending audio data
    process(aud_clock_12)

    Verilog

    always @(negedge(aud_clock_12)) begin
    aud_bk <= aud_clock_12;

    Asignment must be placed outside clock sensitive block, otherwise it won't generate a clock at all

    assign aud_bk = aud_clock_12;
    There's also something wrong with the Verilog PLL instantiation which seems to be mixed with onchip memory.

    pll u0 (
    .clk_clk(CLOCK_50),
    .reset_reset_n(1'b1),
    .clock_12_clk(clock_12pll),
    .onchip_memory2_0_s1_address(ROM_ADDR),
    .onchip_memory2_0_s1_clken(1'b1),
    .onchip_memory2_0_s1_chipselect(1'b1),
    .onchip_memory2_0_s1_debugaccess(1'b0),
    .onchip_memory2_0_s1_write(1'b0),
    .onchip_memory2_0_s1_readdata(ROM_OUT),
    .onchip_memory2_0_s1_writedata(16'b0),
    .onchip_memory2_0_s1_byteenable(2'b11),
    .onchip_memory2_0_reset1_reset(1'b0)
    );

    Regards
    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
the VHLD is almost correctly translated, except for one assignment which apparently misplaced

VHDL

-- Copy the input clock signal
aud_bk <= aud_clock_12;

-- Main process for generating control signals and sending audio data
process(aud_clock_12)

Verilog

always @(negedge(aud_clock_12)) begin
aud_bk <= aud_clock_12;

Asignment must be placed outside clock sensitive block, otherwise it won't generate a clock at all

assign aud_bk = aud_clock_12;
There's also something wrong with the Verilog PLL instantiation which seems to be mixed with onchip memory.

pll u0 (
.clk_clk(CLOCK_50),
.reset_reset_n(1'b1),
.clock_12_clk(clock_12pll),
.onchip_memory2_0_s1_address(ROM_ADDR),
.onchip_memory2_0_s1_clken(1'b1),
.onchip_memory2_0_s1_chipselect(1'b1),
.onchip_memory2_0_s1_debugaccess(1'b0),
.onchip_memory2_0_s1_write(1'b0),
.onchip_memory2_0_s1_readdata(ROM_OUT),
.onchip_memory2_0_s1_writedata(16'b0),
.onchip_memory2_0_s1_byteenable(2'b11),
.onchip_memory2_0_reset1_reset(1'b0)
);

Regards
Frank