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mwac__'s avatar
mwac__
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1 year ago

Issue regarding reading the Analog value from ADC

Hi. I'm working on Altera Cyclone V,SOC DE1 (rev F) board. I need to access the on board available ADC (LTC 2308). The software version I'm using is Quartus ii(13.0,64 bit). The simulation waveform...
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mwac__'s avatar
mwac__
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1 year ago

Well, I genuinely admire the time you've invested in. But the issue I encountered was bit different. Though the test bench generated the exact timing diagram that was required to program an ADC. But when I used the Signal Tap analyzer, it happened to me that the latch of logic 1 was generated at the ADC_DIN pin due to which channel 07 of ADC was selected at the start of each conversion. The difference between test bench and Signal Tap Analyzer behaviour was quite surprising for me. When I modified the code a bit, the Correct channel of ADC has been configured.

Thank You.

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,

Sorry for the delay in replying, was in a 3 day offsite training. Glad that your code is working now, as for your question on the Testbench simulator, I was discussing with my colleague here on this case and we suspect that you might need to add in latency manually to simulate close to real work situation even though the simulated waveform is matching to the one specified in the guide. I wonder whether Terasic would have more information on this since they build the custom DE 1 SOC board.

Thanks

Regards

Kian