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Sudhirkv's avatar
Sudhirkv
Icon for New Contributor rankNew Contributor
5 years ago

Issue in generating the Start of Packet, End of Packet and Empty for the Avalon FIFO Memory Intel FP

Hi All, I am facing the issue while generating the SOP(Start Of Packet), EOP(End Of Packet) and Empty for the Avalon FIFO Memory Intel FPGA IP. Description: Input is applied at the Avalon MM por...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

The ready signal is active, so it's not the downstream component causing the issue. Can you post your IP parameter settings? Maybe you have something configured incorrectly for packetized streaming output.