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Theja's avatar
Theja
Icon for New Contributor rankNew Contributor
2 years ago

Is there any option to generate 100MHZ clock without PLL in max10 device

In our project the external oscillater clock is connected to DPCLK pin max10 cpld. When I try to generate clock using ALTPLL ip .I am getting error like we can't use this pin to drive the PLL clock i...
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Fpga Devkit
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

For Intel Max 10 PLL architecture which provided in the user guide, there are only CLKIN pin that was connected to the PLL input clock. If you refer to this link, https://www.intel.com/content/www/us/en/docs/programmable/683047/21-1/clock-pin-to-pll-connections.html, there is mentioned which dedicated clock pin belongs to which PLL. There is no DPCLK pin there.


There also mentioned in the DPCLK pin's description that it cannot drive PLL inputs.