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Luis_R_Intel's avatar
Luis_R_Intel
Icon for New Contributor rankNew Contributor
7 years ago

Is there a way to include file with macros and small modules without having to use `include in every file?

Using the Quartus Prime software during the analysis and sythesis stage, we get compilation issues due to undefined text macros. The text macros are declared in their own file and used in other files...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Luis,

  1. We need to add the include (macro)files to the project and just compile for Quartus STD & LITE.
  2. For Quartus Pro, the compiler to search for macro file and include it during the compile process. No need to use `include in Verilog module. Please check the attached image

We recommend user to just add the `include "define.v" statement to the start of your design file and add macro file in file list.

Hope it helps! Let me know if you need any further assistance.

Regards

Anand