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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Is it possible to make read and write transaction "simultaneously" using External memory IP(DDR3) on max 10 device ?

Hi, I want to send parallel read and write requests using avalon interface. Since there is only one avalon_ready , avalon_addr signal. Can I perform both the read and write transactions simultaneous...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I don't know of a ready signal with Avalon memory-mapped, only Avalon streaming. Do you mean waitrequest?

Commands can be sent simultaneously from two masters to a memory controller, but arbitration would determine who gets access to a controller while the other master has to wait (with the waitrequest signal). This is handled automatically if you create your design in Platform Designer. You'd have to create arbitration logic yourself if you don't. See the Avalon spec for more details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

#iwork4intel

Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi sstrell,

Yes, avl_ready is same as waitrequest ( in DDR3 IP the former is used).

I want to use same master, not multiple masters. Can I use same master to perform read and write simultaneously?

Thanks