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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Interfacing Nios II and HMC on Cyclone vGT

Hi everyone, Hope all well and I appreciate if you take a look at this and see if you can help us. We are using Cyclone V GT Dev board to test DDR3 HMC controller. We used 32 bit SGDMA to write int...
KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Any updates from you end whether the workaround provided is useful?


Thank you.

Regards,

Kelly


Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Kelly,

I managed to test your suggested workaround and we could get the timing closures by reducing the frequency to 320Mhz and changing speed grade to 8. however, the problem is still there and Nios is not functioning when connecting Nios instruction master to HMC. we did implement on chip memory and nios vectors set to that memory. on BSP editor -linker script we selected .text to be onchip memory and the rest to be fpga_sdram which is HMC. system works fine with no issues. Array of 400MB defined and filled with data and verified. so the question remains why Nios system is unable to boot up/function when instruction master connected to HMC. it appears that connection brings the whole system down. any thoughts ?

thanks and regards,

Aidin.