Interfacing Nios II and HMC on Cyclone vGT

Hi,

The lowest supported frequency for DDR3 is 303MHz, could you try to set to 333MHz in the DDR3RAM for timing closure and see if it works on your end. I speculate that there is some kind of a PLL clock phase time rounding issue.

If not, could you try the workaround as below:

1) Using a text editor open the .qsys file, find the line :

<parameter name="SPEED_GRADE" value="7" />

and change it to match the FPGA part speed grade : in this case 8

<parameter name="SPEED_GRADE" value="8" />

Save the .qsys file.

2) In Quartus : Tools -> QSYS.

Open the .qsys file and click "Generate HDL"

3) Recompile project

Hope this helps.

Thank you.

Regards,

Kelly