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LFahem's avatar
LFahem
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Interconnects resources on Arria 10 FPGA

Hello, I am working with an Attila board on which is installed an Arria 10 FPGA component. In the Arria 10 handbook, there is a diagram of the LAB structure which is atteched below. I want to know w...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

If you disable the hyper-retimer in S10, you've removed one of the key advantages from that device, so I don't trust that number at all.

Length of wires is really not something a designer typically needs to concern themselves with unless, as I said, you start running into congestion issues. Turn on the hyper-retimer and try again.