Interconnects resources on Arria 10 FPGA

Hi,

Thank you for the explanation. However, I think that providing long wires enables the routing tool to overcome some bottleneck problems, espicially in nodes with high fanouts. Actually, I am testing a project design on Arria 10, Cycone 10 Gx, Cyclone 5 and Stratix 10 FPGAs. I have got these results:

• Arria 10 and Cyclone 10 Gx : my project frequency can go until 300Mhz
• Stratix 10 : my project frequency can go until 275Mhz (retiming option is disabled)
• Cyclone 5 : my project frequency can go until 160Mhz

For the Cyclone 5, I can understand the results because it is less performant than Arria10, Cyclone 10GX and Stratix 10. However, I was surprised by the timing results for Stratix 10 FPGA because it has an Hyperflex architecture "with registers everywhere".

When I have checked "Lab diagrams" of each FPGA, I noticed that there is a difference in the routing architecture:

• Arria 10 and Cyclone 10 GX : C4, C27, R3/R3, R32
• Stratix 10 : C2/C3/C4, C16, R2/R4/R10, R24
• Cyclone 5 : C2/C4, C12, R3/R6, R14

So do you think that the length of wires can have a negatif effect on the maximum frequency of a project design on FPGA?

Regards,

Lotfi.