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LFahem
Occasional Contributor
Occasional ContributorInterconnects resources on Arria 10 FPGA
Hello, I am working with an Attila board on which is installed an Arria 10 FPGA component. In the Arria 10 handbook, there is a diagram of the LAB structure which is atteched below. I want to know w...
sstrell
Super Contributor
Super ContributorC: column, R: row
The number specifies how many device resource blocks (LABs, memory, or DSP) the wire route spans. Longer wires are usually more limited and their overuse can lead to congestion issues. You can highlight wire usage for your design using a report in the Chip Planner. The report generates a heat map so you can see where there are "hotspots" of the overuse of certain wire types.
