Intel Stratix 10 MX FPGA HBM issue

I have only one devkit and it shows the calibration failure.

I config a new HBM2 ip and generate its example design. In this project, I add two counters whose clock is hbm_0_example_design_wmc_clk_0_clk and core_clk_iopll_ref_clk_clk respectitively as shown below.

In addition, I add a In-System Sources and Probes Editor to source three reset signals, core_clk_iopll_reset_reset_lxl, hbm_0_example_design_wmcrst_n_in_reset_n_lxl and hbm_only_reset_in_reset_lxl, which are connected to core_clk_iopll_reset_reset, hbm_0_example_design_wmcrst_n_in_reset_n, hbm_only_reset_in_reset ports of HBM2 ip respectitively. And it can probe the above counters, lock signal of PLL and calib status signals.

After programming sof to the board, firstly I give a low > high > low pulse to core_clk_iopll_reset_reset_lxl to enable PLL. Then I drive hbm_0_example_design_wmcrst_n_in_reset_n_lxl be high. Lastly I assert and then deassert hbm_only_reset_in_reset_lxl. The reset sequence is recommended in user guide.

It shows that the two counters can increase normally, and the PLL is locked. But, the local_cal_success is low and local_cal_fail is high.

The frequency of PLL output clock is 250MHz and memory clock frequency is 600MHz.

So the current problem is the example design of HBM2 IP fails to calibrate on Stratix 10 MX FPGA.

I am new in Intel FPGA design so this question would be an easy one for experts.

By the way, are there any other reference designs of HBM2 IP on Stratix 10 MX FPGA?