Forum Discussion

New Contributor

7 years ago

Intel Cyclone 10 LP FPGA Evaluation Kit Revision A2 (EPCQ128A)

Hi, Does anyone know where I can find the new documentation(revision A2), in particular the schematic design for the Cyclone 10 LP FPGA. I have the revision A1 but I can not find the new version re...

JosephC_Intel

Contributor

6 years ago

Hi,

We finally got C10LP Rev A2 posted on Intel official site. Please go to below link:

C10 Main Page:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-lp-evaluation-kit.html

Schematic:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/cyclone10/c10lp-eval-a1-sch.PDF

Thanks,

Joseph

Forum Discussion

Intel Cyclone 10 LP FPGA Evaluation Kit Revision A2 (EPCQ128A)

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work