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DaveMM
New Contributor
New ContributorIn-System Memory Content Editor
Intel Stratix 10 GX FPGA Development Kit L-Tile 1SG280LU2F50E2VG / 1SG280LU3F50E3VGS1 (User guide is not clear) I have configured a ROM to "Allow In-System Memory Content Editor to capture and upda...
sstrell
Super Contributor
Super ContributorIs the data at least correct for the first set of address locations and then the repeated data is incorrect?
It's a long shot but you could try reducing the JTAG frequency (you can go down to 6 MHz) to rule out if this is a JTAG issue.
Related to that, there is a template in the Quartus text editor to add timing constraints for the JTAG interface to your .sdc file. Might want to check that out.
And is your design meeting timing? It could be on the edge, which would explain it working OK functionally but having some issues like this.
