In Quartus cyclone V gx for device ("5CGXC7D6F31C7") we have 480 i/o pin's,

Hi Pavan,

If we follow all pin connection guideline other board design guidelines there should not be signal integrity issues.

Also we can perform signal integrity analysis using your board design determine the FMAX for your system.

Checklist

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an662.pdf

The I/O counts on FPGAs and logic density requirements of designs have increased exponentially. The higher-speed interfaces in FPGAs, including high-speed serial interfaces and memory interfaces, require careful interface design on the PCB. Simultaneous switching noise (SSN) often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system

Follow below link for Simultaneous switching noise.under Assignment->Settings->SSN Analysis

https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/qts/qts_qii5v2_02.pdf

Regards

Anand