New Contributor
New ContributorAttached block diagram illustrates programming of flash using Altera CPLD’s JTAG interface.
Flash is connected to CPLD only and not connected to JTAG interface.
Regular ContributorSince the MAX device offers JTAG boundary scan test access, you could write a test program that, thru the JTAG interface, toggles all the I/Os to the external FLASH device to write data to it, and thus program it.
This would mean coming up with an SVF (or equivalent) bitstream that would be sent down to the JTAG interface by some suitable JTAG host controller. I've forced test engineers to do this before. They complied with my request but were not happy.
Alternatively, you could write a custom CPLD image that interfaces to the JTAG pins (they can be reused as standard I/Os, after all) and performs the appropriate R/W accesses to your external parallel FLASH device. More work for you.
Probably not going to find you can do any of this in the standard Intel/Altera Quartur/MaxPlus software.
