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Altera_Forum
Honored Contributor
14 years agoI'm glad you managed to solve your problem! I was about to suggest to use a scope just to be sure the signals outside the FPGA where the ones you expected.
Solving those kind of problems sure can be painful, but you also learn a lot in the process. The I2C protocol indeed only says that the data line should be stable when the clock signal is high, and one way to do it is to write to sda on the falling edge of the clock (or when you put yourself the clock to 0) and read from sda on the rising edge of the clock (or when you put yourself the clock to 1). It's not 100% compliant when you control yourself the clock because of the delay on the line but in practise it works well.