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Altera_Forum
Honored Contributor
14 years agoI think you should read I2C_sdat instead of sdat in your code, on steps 20, 38, 62 and 63-78. sdat is an internal signal and it is only used to control the output. To read the data pin, place sdat at 1'bz and read the value from I2C_sdat.
When you read the data you should only read it on the rising edge of the clock, the slave will change the data line on the falling edge and you may miss a bit if you read it on both edges. To simplify the code a bit (once it's working ;) ), it seems that most of the time you pull the clock low when step has an odd value and high when it is even. Also in most of the cases you increase step by one. I think you should be able to have those two rules as general ones before the case and just override those on the specific steps that need overriding. Now I'm not a Verilog expert, I'm more a VHDL guy myself, but I think it could be done. As for the register value, did you try to read different registers and see what value you got back?