Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThank you very much for your reply, Daixiwen.
I don't really get it. Do you mean the "generated clock" when you say "generated logic signal"("First using generated logic signals inside FPGAs isn't a good idea.")? I need to generate slower clock because the accelerometer output data rate is 100hz(by default) and my fpga has 50Mhz clock. I will try to remake my program by trying to use always block as less as possible(although I am not sure that I can do it with only a single always block). "Do you actually try to read the acknowledge pulse from the I2C slave? You should read it to be sure it has actually recognized its address on the I2C bus first." Yeah I am actually trying to read ack pulse from ADXL to make sure that the ADXL has already listened the data from master(at 6'd11, 6'd20, 6'd31) and at 6'd40 the master send the ack pulse to the slave.(I believe this is the standard timing diagram for I2C read protocol) Could you give more hint to solve this problem? Thank you so much for your help.