Forum Discussion
Altera_Forum
Honored Contributor
14 years agoFirst using generated logic signals inside FPGAs isn't a good idea. If you have glitches on the signal the FPGA logic could interpret it as a new clock cycle and you would loose some cycles.
It is best to do everything in a single always block and use a counter to generate both the clock and data signals from the same place, changing them only when the counter reaches specific values. Do you actually try to read the acknowledge pulse from the I2C slave? You should read it to be sure it has actually recognized its address on the I2C bus first.