I2C read of De0 nano accelerometer

This is my coding. Please somebody out there help me.

// ADXL clock= 500,000samples of 50Mhz/100Hz

// ADXL address= 0x1D/11101

module ADXL_Read(

clk_50, //clock 50Mhz//

key,

I2C_sclk,

I2C_sdat,

);

input clk_50;

input [1:0] key;

inout I2C_sclk;

inout I2C_sdat;

reg I2C_sdat;

reg [18:0] counter;

reg [18:0] counter2;

reg [1:0] q;

reg [1:0] q2;

wire reset_n;

reg GO;

reg sclk;

reg [6:0] sd_counter;

reg [6:0] slave_add = 7'b0011101; // DEFINE SLAVE ADDRESS

reg [7:0] register_add = 8'b110000; // DEFINE REGISTER ADDRESS

reg [7:0] data; //Data that is read

initial

begin

counter = 3'b0;

data = 8'b0;

end

assign reset_n= key[0];

// 50MHz clock is too fast for the our devive

// therefore slower clk need to be generated

always @(posedge clk_50)

begin

if (counter == 18'b0) // if counter is 0

begin

q = 2'b01;

end

else if (counter == 19'b111101000010010000) // if counter is the desired value(has the same priority as earlier if)

begin

q = 2'b00;

end

else

begin

q<= q;

end

end

always @(posedge clk_50)

begin

if (q == 2'b00)

begin

counter <= counter -1;

end

if (q == 2'b01)

begin

counter <= counter +1;

end

end

//Clk for the Signaltap2

// Notify the moment counter is at the desired value or at 0

always @(posedge clk_50)

begin

if (counter2 == 18'b0) // if counter is 0

begin

q2 = 2'b01;

end

else if (counter2 == 19'b11110100001001000) // if counter is the desired value(has the same priority as earlier if)

begin

q2 = 2'b00;

end

else

begin

q2<= q2;

end

end

always @(posedge clk_50)

begin

if (q2 == 2'b00)

begin

counter2 <= counter2 -1;

end

if (q2 == 2'b01)

begin

counter2 <= counter2 +1;

end

end

// key[0] is to reset the whole operation

// key[1] is to give a start signal

always@(posedge q[0] or negedge reset_n)

begin

if (!reset_n)

GO <= 0;

else

if (!key[1])

GO <= 1;

end

always@ (posedge q[0] or negedge reset_n)

begin

if(!reset_n)

sd_counter <= 6'b0;

else

begin

if (!GO)

sd_counter <= 0;

else

if (sd_counter < 44) //sd_counter maximum

sd_counter <= sd_counter + 1;

end

end

always@ (posedge q[0] or negedge reset_n)

begin

if (!reset_n)

begin

sclk <= 1;

I2C_sdat <= 1;

end

else

case (sd_counter)

6'd0 : begin I2C_sdat<=1; sclk<=1;end

//START

6'd1 : I2C_sdat <= 0;

6'd2 : sclk <= 0;

//SLAVE ADDR+Write(Control Byte)7'b0011101

6'd3 : I2C_sdat <= slave_add[6];

6'd4 : I2C_sdat <= slave_add[5];

6'd5 : I2C_sdat <= slave_add[4];

6'd6 : I2C_sdat <= slave_add[3];

6'd7 : I2C_sdat <= slave_add[2];

6'd8 : I2C_sdat <= slave_add[1];

6'd9 : I2C_sdat <= slave_add[0];

6'd10 : I2C_sdat <= 0; //Write(0)

6'd11 : I2C_sdat <= 1'bz;//Slave ACK

//SUB ADDR(WORD ADDRESS)8'b110000

6'd12 : I2C_sdat <= register_add[7];

6'd13 : I2C_sdat <= register_add[6];

6'd14 : I2C_sdat <= register_add[5];

6'd15 : I2C_sdat <= register_add[4];

6'd16 : I2C_sdat <= register_add[3];

6'd17 : I2C_sdat <= register_add[2];

6'd18 : I2C_sdat <= register_add[1];

6'd19 : I2C_sdat <= register_add[0];

6'd20 : I2C_sdat <= 1'bz;//Slave ACK

//START

6'd21 : begin I2C_sdat <= 1; sclk<=1; end

6'd22 : I2C_sdat <= 0;

//SLAVE ADDR+Read(CONTROL BYTE)

6'd23 : I2C_sdat <= slave_add[6];

6'd24 : I2C_sdat <= slave_add[5];

6'd25 : I2C_sdat <= slave_add[4];

6'd26 : I2C_sdat <= slave_add[3];

6'd27 : I2C_sdat <= slave_add[2];

6'd28 : I2C_sdat <= slave_add[1];

6'd29 : I2C_sdat <= slave_add[0];

6'd30 : I2C_sdat <= 1; //Read(1)

6'd31 : I2C_sdat <= 1'bz;//Slave ACK

//Data read(DATA)

//Data byte 1

6'd32 : I2C_sdat <= 1'bz;

6'd33 : I2C_sdat <= 1'bz;

6'd34 : I2C_sdat <= 1'bz;

6'd35 : I2C_sdat <= 1'bz;

6'd36 : I2C_sdat <= 1'bz;

6'd37 : I2C_sdat <= 1'bz;

6'd38 : I2C_sdat <= 1'bz;

6'd39 : I2C_sdat <= 1'bz;

6'd40 : I2C_sdat <= 1'b1;//Master ACK

//stop

6'd41 : begin I2C_sdat <= 1'b0; sclk <= 1'b1; end

6'd42 : I2C_sdat <= 1'b1;

endcase

end

assign I2C_sclk = (((sd_counter >= 4)&(sd_counter <= 20))|((sd_counter >=24)&(sd_counter <=42)))? ~q[0] : sclk;

endmodule