Forum Discussion
Gerard_M_Intel
New Contributor
7 years agoI have a supplier using the DK-DEV-5CSXC6N. Using the on-board USB-Blaster circuitry they can successfully run debug sessions on both the HPS and the FPGA. However when using an external USB-Blaster not so much.
I have a supplier using the DK-DEV-5CSXC6N. Using the on-board USB-Blaster circuitry they can successfully run debug sessions on both the HPS and the FPGA. However when using an external USB-Blaster ...
YuanLi_S_Intel
Regular Contributor
7 years agoHi GMcSW1,
Apologize that I cannot open the image file. Maybe can u attach it on the forum?
Can you check the following?
[1] Change the switches and jumper to default position.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_cv_soc_dev_kit.pdf (Page 11)
[2] Check whether if the HPS is in JTAG Chain when using USB-Blaster II? To check, simply open SoC EDS Command Prompt and type "jtagconfig".
[3] If it is on the JTAG Chain, try to program the board with USB-Blaster II.
Regards,
YL