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yweid1's avatar
yweid1
Icon for New Contributor rankNew Contributor
6 years ago

I have a problem when I design Max10 using the Quartus (Quartus Prime 17.1) Lite Edition

Hi, I design the Max10m02scu169i7 by the Quartus (Quartus Prime 17.1) Lite Edition,but when I change a parameter in my project,my work didn't work well anymore,as long as I change the parame...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Without knowing what affect the parameter has on the other module, there's no way to really figure out what's going on here. The only thing I can think of is that 60112 requires all 16 bits (0xEAD0) while 112 only requires 8 bits (really only 7 bits; 0x70). So perhaps some type of optimization for this is different between Lite and Standard, though I doubt it. More info is needed. What is not working well with the changed parameter value?

#iwork4intel

yweid1's avatar
yweid1
Icon for New Contributor rankNew Contributor
6 years ago

Thank you for your help!

There is a CRC check in my serial communication receive module ,the CRC will be always wrong when I change the parameters "FPGA_VERSION".And I make sure there are not any connections between the two modules.