Forum Discussion

New Contributor

6 years ago

I can successfully run the design example from PCIe IP guide for A10 devkit, however when I exchang the onchip_memory2_0 component with my own it hangs the PCIe bus.

I can successfully run the design example from PCIe IP guide for A10 devkit, however when I exchang the onchip_memory2_0 component with my own it hangs the PCIe bus. With the MEM component connected...

SengKok_L_Intel

Regular Contributor

6 years ago

Since there are no recent activities, I’ll set this case to close-pending. If you’re still in need of assistance, please reopen this case within the next 20 days

Forum Discussion

I can successfully run the design example from PCIe IP guide for A10 devkit, however when I exchang the onchip_memory2_0 component with my own it hangs the PCIe bus.

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA