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ASing173's avatar
ASing173
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5 years ago

I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

ASing173's avatar
ASing173
Icon for New Contributor rankNew Contributor
5 years ago

its online tool edaplayground (icarus Verilog 0.10.0)

count depends on the inputs given i.e the reset and enable and I am giving both logic so according to that logic the output should be produced...