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ASing173's avatar
ASing173
Icon for New Contributor rankNew Contributor
6 years ago

I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Your testbench is not toggling the clock, so nothing is going to happen.

#iwork4intel

  • ASing173's avatar
    ASing173
    Icon for New Contributor rankNew Contributor
    6 years ago

    thanks I will check with that.....