Contributor
ContributorHi have seen in the doc that the stratix 3 does not support clear/preset implementation:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51006.pdf
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Register Control Signals Avoid using an asynchronous load signal if the design target device architecture does not include registers with dedicated circuitry for asynchronous loads. Also, avoid using both asynchronous clear and preset if the architecture provides only one of these control signals. Stratix III devices, for example, directly support an asynchronous clear function, but not a preset or load function. When the target device does not directly support the signals, the synthesis or placement and routing software must use combinational logic to implement the same functionality. In addition, if you use signals in a priority other than the inherent priority in the device architecture, combinational logic may be required to implement the necessary control signals. Combinational logic is less efficient and can cause glitches and other problems; it is best to avoid these implementations.
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So I have been looking further into it:
Synplify implements the clear/preset flip flop into a latch + a FF, preventing the timing analysis to be done and preventing combinational loop at quartus level timing check.
This makes those huge non sense delays to be absent.
Quartus synthesis implements as a normal FF with combi logic, this lead to non sense timing routing and analysis.
Would it be possible to tell quartus to implement a latch to solve this issue?
We won't change the RTL code, we use the code for the chip and never write specific FPGA code.
See an attachments with pictures showing this.
