huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

I have been looking further into this,

apparently Quartus 19.3, for the Arria X FPGA,

has issue with clear/preset/clk constructions, that gives a combi loop (but not the case with quartus 13.1 and the stratix 3):

Example below:

if (!cd) q <= `unitdelay 1'b0;

else if (!sd) q <= `unitdelay 1'b1;

else q <= `unitdelay d;

end

Combi loop in the timequest analyzer:

Found combinational loop of 3 nodes

Node "rfd_ic_i|u_top|u_core|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|read_fail_sync_reg|q~1~la_mlab/laboutt[6]"

Node "rfd_ic_i|u_top|u_core|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|read_fail_sync_reg|q~1|dataf"

Node "rfd_ic_i|u_top|u_core|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|read_fail_sync_reg|q~1|combout"

Note the presence of the la_mlab/laboutt[6] again.

How to solve this issue, keeping the same RTL code?

Second (vhdl) example:

process(scl_clk_n, rstn, start_stage1,scantestmode)

begin

if(rstn = '0') then

start_stage2 <= '0' after delay_f;

elsif(start_stage1 = '1' and scantestmode = '0') then

start_stage2 <= '1' after delay_f;

elsif(scl_clk_n'event and scl_clk_n = '1') then

start_stage2 <= '0' after delay_f;

end if;

end process;

Found combinational loop of 3 nodes

Node "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_detect_inst|start_stage2~1~la_mlab/laboutt[0]"

Node "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_detect_inst|start_stage2~1|dataf"

Node "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_detect_inst|start_stage2~1|combout"