Forum Discussion
New ContributorHPS Avalon Master Addressing Issue!
Super ContributorI'm a little confused by your question. You set the base address in Platform Designer so that a component, like the HPS, can access your custom IP, just like the PIO off-the-shelf IP. Generating the system creates the files needed (the software handoff files) that make it possible for a software developer to access the hardware. Are you trying to create a bare-metal application? What is your target device here (since the flow is different for different families)?
Maybe if you post some or all of the HDL of your custom component, that would better help understand the issue.
For your questions:
1) One of the main ideas of PD is that individual signals are bundled in the interfaces, so you don't need to really think about them until you're creating your own custom IP that makes use of these standard interfaces, like Avalon memory-mapped. As such, yes, the signals are there. To easily see the individual signals, select a component in your system design, open the Block Symbol view, and enable the Show signals option.
2) For off-the-shelf IP, you'd look in the user guide for the IP, including the embedded IP peripherals guide for register maps. For custom IP, you build the register map yourself and, as I mention, set the base address in the tool. When you generate the system, HTML reports are generated with register maps and other information. Look in the folder named after your system design to find the generated documentation.
Hope this is useful as a start.
#iwork4intel
AAjit2I'm a little confused by your question. You set the base address in Platform Designer so that a component, like the HPS, can access your custom IP, just like the PIO off-the-shelf IP.
Yes this is correct, as part of accessing it I assigned it an address (0x0007_0000)
Generating the system creates the files needed (the software handoff files) that make it possible for a software developer to access the hardware. Are you trying to create a bare-metal application? What is your target device here (since the flow is different for different families)?
Alright, so the board I'm using is the DE0 Nano SoC which has the FPGA and the HPS system in it. What I'm trying to do is to communicate to a custom IP with HPS as master and FPGA as a slave. To do this I'm utilizing the Linux system on HPS to run a C compilation. Hope this clears that
For your replies:
1) Yes, I'm aware that the signals are bundled together under the interface and I can see them, what I want to know is how I can access them as a Master. So say I have an avalon slave interface with write, writedata, readdata etc. What address do I use on the Master side of things to access the individual signals, because as I understand it, the master/slave needs to have them for the data transfers to take place. The address in this instance refers to the interface as a whole, should I and do I need to address individual signals for the data transfer to take place?
2) For off-the-shelf IP, you'd look in the user guide for the IP, including the embedded IP peripherals guide for register maps. For custom IP, you build the register map yourself and, as I mention, set the base address in the tool. When you generate the system, HTML reports are generated with register maps and other information. Look in the folder named after your system design to find the generated documentation.
2) So are you saying the HTML reports would contain the register address information with which I can access them from the HPS Master? From what I have seen, they only include the declarations and signals but not the address details that'll help me to access individual registers.
- sstrell
"1) Yes, I'm aware that the signals are bundled together under the interface and I can see them, what I want to know is how I can access them as a Master. So say I have an avalon slave interface with write, writedata, readdata etc. What address do I use on the Master side of things to access the individual signals, because as I understand it, the master/slave needs to have them for the data transfers to take place. The address in this instance refers to the interface as a whole, should I and do I need to address individual signals for the data transfer to take place?"
Again, the address is set in Platform Designer and conveyed to software through the handoff files, including .sopcinfo. I don't understand what you mean by addressing to access the individual signals. If you do a write to address 0x70000, your custom component, the appropriate signals are enabled by the interconnect to perform the write at that address (write is enabled, data is put on writedata, address is set to appropriate address) and your component must be capable of taking these input signals and storing the data at the appropriate location (its own address 0x0000). If your component is, say, a 32-bit component, to get to the next register location in it (slaves use word addressing based on their data bus width), you'd increase the master address by 4 (byte addressing), so the master would need to access address 0x70004.
Let me know what you think about this.
#iwork4intel
- AAjit2
By individual signals I meant the write, byteenable etc. but you cleared that up when you said the system generates it. I've tried again with the address and it works now. So thank you for that.
The only issue is the sizing. So say I want to read back the data from the FPGA slave to the HPS master but the FPGA slave register is say 256 bits and the master pointer is 64 bits. I presume this is also an instance where the slave address incremented by 4 (or in this case maybe
comes in to access the next set of data? For some reason when I try to do that it doesn't show me the next set. What am I missing?
