Forum Discussion
YigalB
New Contributor
New ContributorHow to use reset input in DE10 lite design?
I assume the DE10 Lite board state can't be assumed after power up and also it should be a better practice to use reset signal - also for the simulator. Can someone provide me a design example with ...
Deshi_Intel
Regular Contributor
Regular ContributorHi Yigal,
I understand your intention now but sorry, the feature request is not available on DE10 board.
DE10 lite board is just simple demo board meant to showcase FPGA feature and capability. The board is not designed to fit into real system design application.
For your enquiry on FPGA FF,
- If you are designing your own FIFO logic, then you should be able to configure the default state yourself
- Else if you are using Intel FPGA FIFO IP core then it will has its own control mechanism where you can read more about it in below link
You can simply google for Intel FPGA IP core user guide to find out more about its usage.
Thanks.
Regards,
dlim
YigalBNew Contributor
New ContributorWhen I mentioned FF i meant FlipFlop, not FIFO.
I was wondering if registers are always committed to be zero after image is loaded and start to run.
