Forum Discussion

Veerappan's avatar
Veerappan
Icon for New Contributor rankNew Contributor
1 year ago

How to use FPGA-to-hps free clock as HPS clock source?

Hi, In our custom board, an external oscillator is working but the PLL lock does not happen, so we decided to use FPGA-to-HPS free clock or HPS internal clock. We enabled FPGA-to-HPS free **bleep...
Board Debug
KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Veerapan,

Was discussing your issues with our team here, could you help provide all the error logs that you see when booting (including the pll unable to lock) and also from your screenshot, there is 3 warnings on the bridges, could you confirmed the connections to the bridge is there?

something like this example that I saw in another case on the bridge connections

https://community.intel.com/t5/Programmable-Devices/Enabling-HPS-FPGA-bridges-on-Agilex-7/td-p/1631179

In addition, could you provide us with the design files as well?

Thanks

Regards

Kian