How to use FPGA-to-hps free clock as HPS clock source?

Hi Veerappan,

Apologies for the long delay in replying , was on medical leave for 2 weeks and my forum account access got revoked, just manage to regain access this week.

I will look into this case and feedback to you later, once again I'm sorry for the long response delay.

Thanks

Regards

Kian

Hi Veerapan,

Was discussing your issues with our team here, could you help provide all the error logs that you see when booting (including the pll unable to lock) and also from your screenshot, there is 3 warnings on the bridges, could you confirmed the connections to the bridge is there?

something like this example that I saw in another case on the bridge connections

https://community.intel.com/t5/Programmable-Devices/Enabling-HPS-FPGA-bridges-on-Agilex-7/td-p/1631179

In addition, could you provide us with the design files as well?

Thanks

Regards

Kian

Hi ,

May I know the status of this case, whether you could provide more information on this?

Thanks

Regards

Kian

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

But to illustrate again , do follow these steps

1. Enable the FPGA-to-HPS Free Clock: In the input clocks tab, enable the FPGA-to-HPS free clock. This will allow you to use it as a clock source (which enabled but just reconfirm)

2. Select the Clock Source: Choose the FPGA-to-HPS free clock as the source for the main and peripheral reference clocks in the internal and output clock tab in the HPS IP (which already enabled but do confirm this)

3. Configure the PLL: Ensure that the PLL (Phase-Locked Loop) is properly configured to lock onto the FPGA-to-HPS free clock. This might involve setting the correct parameters for the PLL to achieve a stable lock.

4. Check Connections: Verify that all connections to the HPS-FPGA bridges are correctly configured. This includes ensuring that the bridges are enabled and properly connected.

5. Debugging: If you encounter issues such as the PLL not locking, check the error logs and warnings related to the bridges and clock configurations.

Thanks

Regards

Kian