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Veerappan's avatar
Veerappan
Icon for New Contributor rankNew Contributor
11 months ago

How to use FPGA-to-hps free clock as HPS clock source?

Hi, In our custom board, an external oscillator is working but the PLL lock does not happen, so we decided to use FPGA-to-HPS free clock or HPS internal clock. We enabled FPGA-to-HPS free **bleep...
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KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
9 months ago

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

But to illustrate again , do follow these steps

  1. Enable the FPGA-to-HPS Free Clock: In the input clocks tab, enable the FPGA-to-HPS free clock. This will allow you to use it as a clock source (which enabled but just reconfirm)

  2. Select the Clock Source: Choose the FPGA-to-HPS free clock as the source for the main and peripheral reference clocks in the internal and output clock tab in the HPS IP (which already enabled but do confirm this)

  3. Configure the PLL: Ensure that the PLL (Phase-Locked Loop) is properly configured to lock onto the FPGA-to-HPS free clock. This might involve setting the correct parameters for the PLL to achieve a stable lock.

  4. Check Connections: Verify that all connections to the HPS-FPGA bridges are correctly configured. This includes ensuring that the bridges are enabled and properly connected.

  5. Debugging: If you encounter issues such as the PLL not locking, check the error logs and warnings related to the bridges and clock configurations.

Thanks

Regards

Kian