How to trigger PAM-4 signal from Stratix 10 TX SI kit?

Hie,

Please check my replies to your questions above:

1. To be able to observe PAM4 signals you will need to use a Real Time Scope (RTS) or Sampling Oscilloscope that support PAM4. The Rx architecture is different between NRZ and PAM4, hence you should be using a DCA that supports PAM4. As for whether external clock is required; RTS don't require external clock but some sampling scopes require it. However, the newer sampling scopes has a build in clock recovery module that don't require external clock trigger (typically sourced from the reference clock to Tx PLL or recovered clock from CDR). Please refer to your scope's applications notes on measuring PAM4 signals to understand if external clock source is needed. Also, due to non-linearity of the PAM4 eye's, you will need some level of soft equalization or FEC (typically soft feature in the scope) to be enabled to observe a clean eye. Please check this in the scope application notes on what to enable to observe the eye.

Regards,

Nathan

Replies to remaining questions:

2. Could you attach the scope snapshot so I could understand further whether its showing the signal tri-stated or not. If you turn off the channels using toolkit, the channels are not powered down but tri-stated.

3. Yes. this is the method to choose which device (MAX V or Stratix 10 ) to program. Yes, after selecting the correct SW setting, then you can program the device using Quartus Programmer.

Regards,

Nathan

Hello Nathan,

Thank you for your reply. We are able to create 25GBaud PAM-4 signals with a high-speed DAC and display eyes on our DCA without problems. (I have access to two DCAs that can do this and have tried both.) Our DCAs are not bleeding edge technology but still seem sufficient. The main constraints are (1) that the trigger cannot be too fast (I believe 2 GHz is the limit, I don't remember) and (2) the symbol rate should be an _exact_ multiple of the trigger signal rate. Because of this constraint, we've tried applying an external clock with a rate which divides the symbol rate to the various PLL clock inputs on the SI board, including the one for the specific e-tile that generates the SMA outputs (9A as I recall). We still can't get the signal to trigger. It's not just a matter of having a closed eye. We've tried external clocks in the 100-156.25 MHz range. I wonder if maybe our 500 mV input clock signal is too low? We are driving it single-sided, not differential. By the way, as you suggest, I can capture traces with a real-time scope, but this is not what we want. Thank you again for the help.

I believe the limitation is on the scope trigger limitations.

Well, I used the "ClockController.exe" app and changed clock 0 from 156 to 176 MHz; that apparently solved the problem. I suggest including some triggering instructions in the next release of the "Quick Start Guide."

Hie,

It seems your issue was related to the frequency for the clock generated from the Stratix 10 TX development kit was not correct. I should have pointed you to the Development Kit's user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-tx-devl-kit.pdf

The information on the ClockController is covered in section 5.3.11. Anyway will provide feedback to consider incorporating information about configuring the clock controller frequency in the Quick Guide.

Regards,

Nathan

Yes, OK, thank you. That would be helpful to people, surely. I guess my thinking was that the BTS and the design examples would work "out of the box," so to speak. The Quick Start Guide certainly gives that impression. In any case, thank you for the help.

Yes, Thanks for your feedback as well.