Forum Discussion
How to transfer data from FPGA to HPS DDR
- 3 years ago
After testing, using the mmap function on the HPS side can read data from HPS DDR. I referred to https://github.com/zangman/de10-nano/blob/master/docs/FPGA-SDRAM-Communication_-Avalon-MM-Host-Master-Component-Part-3.md and used the mmap function to operate on HPS DDR, resulting in the same results as Zangman's.
In cycloneV soc(de10-nano), the starting address of HPS DDR is 0x0000000 and the ending address is 0x3FFFFFFF.
/* code for operating HPS DDR */ #include <stdio.h> #include <stdlib.h> #include <fcntl.h> #include <sys/mman.h> #define HPS_DDR_BASE 0x00000000 #define HPS_DDR_SPAN 0x40000000 #define HPS_AXI_BASE 0xC0000000 int main() { int fd; void *hps_ddr_base; void *h2f_base; int *addr1; int *addr2; // Open /dev/mem device fd = open("/dev/mem", O_RDWR | O_SYNC); if (fd == -1) { perror("could not open /dev/mem\n"); return 1; } hps_ddr_base = mmap(NULL, HPS_DDR_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, fd, HPS_DDR_BASE); h2f_base = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, HPS_AXI_BASE); if (hps_ddr_base == MAP_FAILED) { perror("could not mirror HPS DDR3 to user space\n"); close(fd); return 1; } // Write 0xAA to 0x20000000 addr1 = (int*)(hps_ddr_base + 0x20000000); *addr1 = 0xAA; // Write 0x1 to 0xC0000000 addr2 = (int*)(h2f_base); *addr2 = 0x1; // Unmap and close the /dev/mem device munmap(hps_ddr_base, HPS_DDR_SPAN); close(fd); return 0; }Thank you again for your help. Please close this thread, Adzim.
Regards.
Hello,
I'm Adzim will assist you in this thread.
Based on my understanding, you want to use DDR interface that connect to HPS and want to know how to send the data from FPGA side to DDR interface in HPS side.
In that case, the HPS IP has a port "f2h_sdram" that can transfer the data into the SDRAM.
You need to connect the port with the Avalon Memory Mapped Master or AXI such as mSGDMA module.
Sorry, we don't have an example design for HPS DDR.
But I think you can check on other example design such mSGDMA example design for a showcase the use of mSGDMA. https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335
Anyway, you can find all reference design available in FPGA Design Store in Intel website. https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html
Regards,
Adzim
- 22584323 years ago
Occasional Contributor
Hello Adzim,
Thanks for your help. I have referred to writing_to_hps_memory and made modifications to my design. As you said, I used F2H_ SDRAM bus, but my confusion is how to control mSGDMA to transfer data into HPS DDR through the F2H_SDRAM bus. In writing_to_hps_memory ,control mSGDMA by writing a program on the HPS side. However, I need to write a program on the HPS side to send data from HPS DDR. Therefore, I want to add a nios II in qsys (platform designer) to control mSGDMA for data transmission. I don't know if this is feasible.
If possible, could you tell me some details about mSGDMA, such as how I should operate it for data transfer.
Best regard.
platform designer