how to read data from FIFO in SOPC

BadOmen,

thanks for your reply~

you said :" Also I take it that 'outen' is wired up to 'slread & ~rdempty",yes, it is right,I have changed my code:

rdreq(sl_read & sl_chipselect & out_en & (~rdempty) ), to rdreq(sl_read & out_en & (~rdempty) ).

thanks to you,now,I can read data correctly from the FIFO ,next ,I want to translate those data to the SDRAM by DMA component,when I add the DMA component to my SOPC system , there are several errors when generating SOPC system in SOPC builder,I have rebuild my SOPC system many times,but the errors always existed...

the following are the errors:

CPU/instruction_master:Base Address for dma_0/control_port_slave must be a multiple of its span 0x40;

CPU/instruction_master:Base Address for sys_clk_timer conflict with pll;

CPU/instruction_master:Base Address for jtag_uart must be a multiple of its span 0x40;

......

I add the DMA conponent at last ,the address of it would not be conflict with other components ,but there is the error,I donnot know the reason?

the conflict between 'sys_clk_timer' and 'pll'

the conflict between sys_clk_timer' and 'sysid'

and something of this kind are also generated,I have try to changed the base_addresses of them manually and try to get the answer using the internet,but I cannot make it ,so I turn to your gurus help me, thanks~

best regards