how to read data from FIFO in SOPC

The chipselect and read signals are generated by the fabric that connects to your slave port. These are what tell your component that it's being read. Chipselect is a bit redundant since it's going to assert at the same time as read. So when the Nios II core performs the read access to your FIFO slave port you should see the read and chipselect assert 0 or more cycles (dependent on your system topology) after the CPU asserts the read signal.

You have a read request signal so it looks like you are using the FIFO in legacy mode. I recommend putting it into lookahead mode which means that any time empty is low there is valid data at the output of the FIFO.

aclr is the asynchronous reset for the FIFO so it's not really dependent on anything. For timing reasons I can see it being a good idea to assert aclr in sync with the write clock. If it fails timing Timequest will let you know by showing recovery or removal violations.