How to make RSFEC IP work in Stratix10 device?

HI, Yes, these are the answers that I am looking for. Do you had a chance to try out with 100G Eth example design to see if the issue still persist ? Also, do take note that RS-FEC block had extra IO PLL to clock it. I presume you had provided correct input clock to the 100G IP, clk_ref pin ? Can you probe reg address 0x322 PHY_CLK bit[2:1] to see whether RS-FEC PLL is locked ? Expected value of 1 Lastly, do you still encounter this issue when internal loopback is disabled (meaning normal external data traffic transaction) ? Thanks. Regards, dlim