How to generate 3 DW Memory TLP to PCIE Card on Cyclone 4 GX board?

Hie, Please check my replies to your question: Question: initially the PCIE Card on Development board was not detected even for example designs of Quartus 18.1 version, (i doubt the free_100MHz clock pin which i give to pll clock), Please suggest me what could be the issue. Answer: There could be multiple reasons for this such as: i. refclk with SSC not supported when using seperate refclk architecture - you mentioned you are supplying 100MHZ clock pin. Hence, does this mean the root port(CPU) and endpoint (FPGA) have separate refclk. If yes, most motherboards refclk have SSC and Cyclone IV cannot handle SSC for separate refclk architecture ii. reference design or functional driver issue - the reference design provided with the Development Kit has been tested with both Windows and Linux OS. However, there could be OS software versions which could experience compatibility issues. Also, if the example design is updated from an older Quartus version, this could require some connectivity changes in RTL. Is this design created by updating an Example Design created in Quartus 10.1? iii. FPGA programmed (configured) to early or too late that enumeration was not successful the first time due to missing the PCIe link up time requirement. This can typically be resolved via a warm reboot. There could be other reasons. Hence, to really understand the reason, we need to debug the issue. Please advice on the following: i. Can this issue be fixed via cold/warm reboot ii. Can you please check the following signals in STP (Quartus Signaltap) and provide the snapshot after OS reboot. - ltssm - pll_locked - rx_signaldetect - rxlocked_to_data iii. Could you provide details on the source of the reference design used? Question: Example design of 10.1 Quartus version is working, now i want to generate some memory TLP to check the application layer that i have generated, i have used pcie tree, but in signal tap i couldn't see any waveforms, once i stop running i see some message tlp data in rxdata, rxbardec=01, rx_be=0f. Answer: Intel-PSG's PCIE solution does not cover the Application layer software development. The IP generated in Quartus only provides the PCIe PHY, DLL and TL configuration together with an interface bridge (AVST or AVMM or AVMM-DMA). Intel-PSG also provides a main driver as part of the Quartus generated IP. Hence, it is for users to create their own functions and software applications. The example design with the Development Kit has a very basic driver with simple API to only generate a few message TLP, To write 3DW TLP, user will need to create the Application Layer and use their own functional driver. The most simple method to do this is use a third party PCIE Device driver development tool. Question: Please send me if any detailed guidelines are present for sending 3DW memory TLPs from PCITree. Answer: My apologies, as mentioned above, this needs to be done in Application layer and Intel-PSG does not document this. Regards, Nathan