How to enable TX and RX in 100G MAC and PMA for E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IP s

Hi,

I don't quite get your question but you can always refer to the user guide doc parameter control explanation table on page 51 onwards for detail

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-etile-hip-ethernet.pdf

Thanks.

Regards,

dlim

HI,

I have not hear back from you for close to 2 months

Hopefully the guideline in user guide doc is able to clear your doubt.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim