Vicky1Regular Contributor6 years agoHi, It seems to be a bug for Q18.0 Pro, please try to use Quartus 18.1 Pro or later version for vwf files.Regards,Vicky
Recent DiscussionsSyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series designPCIe Root Complex on DK-A5E013BM16AEAAgilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_AlteraAgilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPsR-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work
