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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

how to configure Cyclone10 input clk and PLL

Hi, The model I am using is Cyclone10LP 10CL120. how to instantiate PLL by verilog code way? how to instantiate PLL by block design way in quartus?
Fpga Devkit
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 months ago

Great to hear that, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.