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xli32's avatar
xli32
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7 years ago

How to choose the voltage level of MSEL pins

Hi, I am a new learner of FPGA and designing a FPGA hardware using Cyclone 10 LP. If I want to load the .jic to EPCS16 using JTAG, is it needed to connete the MSEL[3..0] as 0010? The handbook sugges...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
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7 years ago

Hi xli32,

I have checked, the MSEL pins are require to be hardwire the MSEL pins to VCCA (2.5V) or GND without pull-up or pull-down resistors. This has been clearly stated in the Cyclone 10 LP device handbook. Please do not be confuse between configuration voltage standard (for example 3.3V/3.0V) and the MSEL pin connection to VCCA. The configuration voltage standard refers to the voltage level applied to the VCCIO supply of the bank in which the configuration pins reside in.

Regards,

Nooraini

  • xli32's avatar
    xli32
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    7 years ago

    OK, thanks a lot!

  • oiglesia's avatar
    oiglesia
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    5 years ago

    Hi Noraaini_Y_Intel,

    I came across this old post and I actually have a related question. The configuration pins are split between 4 banks in the Cyclone 10 LP, namely banks 1, 5, 6 and 8.

    What happens if different VCCIO voltages are applied to those banks? For example, let's say banks 5 and 6 are used for PCI (and are therefore supplied with VCCIO=3.0V), whereas the rest use the 3.3V-LVCMOS standard. Which configuration voltage standard should be chosen in that case, 3.0V or 3.3V? Or, in fact, all I/O banks containing configuration pins must use the same VCCIO level? I haven't been able to find any mention to such case in the documentation so far.

    Thanks and have a great day