How to boot board from EPCS with NIOSII code running from SDRAM?

Hi Hareesh,

Thanks for your advice.

My first demo which the nios ii code runs on on-chip memoy: I followed the steps in the video, combined the .elf into .sof, convert it to .jic, and run successfully without problem.

However, the second demo(DE0_NANO_SDRAM_Nios_Test provided by Intel) which the nios ii code runs on external SDRAM memory: I tried to follow the steps, in the SDRAM contoller of the qsys system, I can't find the two options to check in the "Memory Initialization", as shown in this screenshot, do you have any idea?

Thanks again.

Hi,

I attached the complete DE0_NANO_SDRAM_Nios_Test project here, you can open to see the platform design file clearly.

Or please help check if the nios ii code is really runs on external SDRAM.

Thanks again.

Hi hareesh,

Actually the design is provided by Intel as I said in my first thread, this is the original source: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479

And I opened the design with Quartus lite v18.1, I can see the SDRAM controller without any problem.